A close look at the M5 and M6 chips reveals big changes in design at the 2-nanometer level, allowing Apple to significantly improve the performance of the M6.
The M6 introduced with the Mac mini in August is the first desktop-class Apple chip using a 2-nanometer fabrication process. The change, which means Apple can make the chips denser, has resulted in big improvements in terms of performance.
Die shots posted to YouTube by High Yield and SemiAnalysis offer a glimpse into the changes Apple made to the chip's design.
The die shrink means there's a physical difference in size between the generations. The M5 is made on a 12.75mm by 12.08mm sliver of silicon, occupying 154 square millimeters, using TSMC's N3P process node.
The M6 is much smaller, at 12.8mm by 11.06mm, giving it only 141.6 square millimeters to play with. However, since it uses the N2 process node, it can fit more into a smaller space.
Same, but different
The analysis points out that while there's some similarities between the M5 and M6 layouts, there are many differences. The first obvious similarity is the memory interface, which is arranged at the top of each die.
The 16GB DRAM model of the M6 has the same 9,600 megatransfer per second DRAM as the M5, giving it the same memory bandwidth. The 24GB and 32GB memory M6 models have the increased 170GB/s memory bandwidth due to using faster 10,667-megatransfers DRAM instead.
A GPU cluster is located below the memory, but with the M6 having a clearly different structure due to having two more GPU cores on hand. However, the die shrink also means the GPU cores on the M6 are about 10% smaller than the M5.
Below that is the same 16-megabytes of System Level cache across both generations.
Core changes
We already knew Apple changed the CPU section, with Apple moving from four super cores and six efficiency cores in the M5 to two super, four performance, and six efficiency cores in the M6.
Looking at the M6 die shot, the two S-cores are quite large, similar to the M5, and each have their own slice of L2 cache, too. That cache is also larger, at 1.5 megabytes per core.
The new M6 S-cores are, again, smaller than the M5 versions, even with their individual L2 caches being 50% larger.
Die maps of the M5 [left] and M6 [right] - Image Credit: High Yield, SemiAnalysis/YouTube
That said, the two cores are also connected to two large shared L2 caches, but it's unusual in design. Both shared caches are 10 megabytes in size, which is a combined 4 megabytes more than on the M5.
However, one appears to be made with an 80-kilobyte SRAM macro, referring to blocks of memory.
While Apple has also reduced the super core count in favor of more performance cores, the four P-cores are connected to those same shared caches. It's a combined cluster, rather than the cache being limited to just one of the two core types.
The efficiency or E-core cluster is still separate, just like the M5. The M6 version is, again, arranging six cores around 8 megabytes of shared cache, up 2 megabytes from the M5.
Apple also includes an AMX unit for the E-core cluster. This refers to the Apple Matrix Coprocessor, used to help with matrix math.
Neural Symmetry
As seen with the A20 Pro, Apple's Neural Engine is now double in size when it comes to core counts. However, rather than being jammed into whatever space was available on the A20 Pro, the M6 version takes a more symmetrical approach.
Shown in the die shot as a sideways T, the cores are shown to be split into two clusters, each made up of eioght dual-core sections. The two sides have their own caches, before converging in a central control area.
Along the bottom, the I/O of the chip hasn't changed much, but there are some PCI-Express lanes, specifically the physical layers (PHYs).
There are the same four-lane display PHY as well as a seven-lane camera PHY. But the high-speed PHY lanes are shown to use the same designs across all six of the PCI-Express lanes.
The PHY lanes for PCI-Express also appear to be the same as the ones used for Thunderbolt PHYs. The analysis believes this could be six lanes of PCI-Express Gen 4.
This is a big improvement over the M5, which used three lanes of PCI-Express Gen 4 and two more of PCIe Gen 3.
Looking to M7
The current belief is that the M6 generation will be a shorter one than usual, with Apple expected to move to the AI-centric M7 within months. There will almost certainly be more changes to the chip designs for that generation.
The analysis proposes that a big one will be Apple changing the memory interface. It's been the same 128-bit interface it's used since the M1.
The A20 and A20 Pro hint at this as a possibility, as each use a wide 96-bit interface. Since the M-series chips are fundamentally based on their mobile counterparts, this could be a change coming along with the next generation.